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Cypress Semiconductor /psoc63 /BLE /BLESS /EFUSE_TIM_CTRL1

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Interpret as EFUSE_TIM_CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCLK_HIGH0SCLK_LOW0CS_SCLK_SETUP_TIME 0CS_SCLK_HOLD_TIME 0RW_CS_SETUP_TIME 0RW_CS_HOLD_TIME

Description

EFUSE timing control register (common for Program and Read modes)

Fields

SCLK_HIGH

Decides the duration of TPGM (in Program mode) or TCKHP (in Read mode) TPGM: Burning Time TCKHP : SCLK high Period
SCLK_LOW

Duration of SCLK LOW (TCLKP_R) or TCKLP_P
CS_SCLK_SETUP_TIME

This register specifies the setup time between CS and SCLK (TSR_CLK)
CS_SCLK_HOLD_TIME

This register specifies the hold time between CS and SCLK (THR_CLK)
RW_CS_SETUP_TIME

This field decides setup time between RW & CS (TSR_RW: in read mode) or RW & AVDD (TSP_RW: in Program mode). TSR_RW: RW to CS setup time into Read mode TSP_RW: RW to AVDD setup time into program mode
RW_CS_HOLD_TIME

This field decides hold time between RW & CS (THR_RW: in read mode) or RW & AVDD (THP_RW: in Program mode). THR_RW: RW to CS hold time out of Read mode THP_RW: RW to AVDD hold time out of program mode

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data